The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
Recently, nanosheet devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). Nanosheet devices provide a channel in a stacked nanosheet structure, which allows gate structures to extend around the channel region providing access to the channel on two or four sides. In other words, the nanosheet structure increases the effective gate width in a transistor device. Nanosheet devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. The increased effective gate width may come with a tradeoff in a reduction of (110) plane. However, for p-type field effect transistors (FETs), a (110) plane provides the highest mobility for holes than other crystallographic planes (e.g., (100), (111) planes). Therefore, p-type FETs may not benefit as much as n-type FETs from a nanosheet structure. Accordingly, while the nanosheet configuration have been satisfactory in many respects, challenges with respect to performance of the resulting device may not be satisfactory in all respects.